The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.50 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.50 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region, or gate electrode. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown). After photolithography, etching is then conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and lid with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed, to effect planarization. Planarization, as by CMP, is then performed.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.50 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature. Such a conventional technique is illustrated in FIG. 3, wherein metal feature 30 of a first patterned metal layer is formed on first dielectric layer 31 and exposed by through-hole 32 formed in second dielectric layer 33. In accordance with conventional practices, through-hole 32 is formed so that metal feature 30 encloses the entire bottom opening, thereby serving as a landing pad for metal plug 34 which fills through-hole 32 to form conductive via 35. Thus, the entire bottom surface of conductive via 35 is in direct contact with metal feature 30. Conductive via 35 electrically connects metal feature 30 and metal feature 36 which is part of a second patterned metal layer. As shown in FIGS. 2 and 3, the side edges of a metal feature or conductive line, e.g., 30A, 30B, and 36A, and 36B, may taper somewhat as a result of etching.
The reduction of design features to the range of 0.50 microns and under requires extremely high interconnect density. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height of the through-hole with respect to diameter of the through-hole. The resistance of the via rises rapidly with decreasing cross section, adding more incentive to make the via as large as feasible. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via", which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate, causing a short. For example, adverting to FIG. 4, first dielectric layer 41 is formed on substrate 40 and a first metal pattern comprising a first metal feature, e.g., metal line 45, is formed on first dielectric layer 41. The intervening spacing gap is filled with SOG 42. Dielectric layer 43 is then deposited and a through-hole formed therein exposing a portion of the upper surface and at least a portion of a side surface of first metal feature 45 and exposing a portion of SOG 42. Upon filling the through-hole with a metallic plug 44, typically comprising an initial barrier layer (not shown) and tungsten, penetrates through to substrate 40, as a result of "spiking" which occurs during the via etch, thereby causing shorting.
Another problem generated by reducing the size of metal lines below about 0.50 microns is that it becomes increasingly difficult to voidlessly gap fill interwiring spacings with a dielectric material, such as SOG. Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. for intermetal applications.
However, the use of HSQ presents problems, particularly in borderless via applications. Typically, when forming a borderless via, plasma etching is conducted. However, it was found that the plasma etch rate of HSQ is considerably faster than traditional deposited oxides typically deposited on a dielectric gap fill layer, such as a silicon oxide derived from tetraethyl orthosilicate (TEOS) or from silane by plasma enhanced chemical vapor deposition (PECVD). Accordingly, during plasma etching to form a misaligned through-hole for a borderless via, the etch rate of the HSQ gap fill layer accelerates, thereby producing large trenches along the side surfaces of the metal lines. For example, adverting to FIG. 5 a first patterned metal layer comprising metal features 51A and 51B separated by gap 52 is formed on dielectric layer 50. A layer of HSQ 53 is deposited filling the gaps in the patterned metal layer. A layer of a dielectric material 54, such as silicon oxide derived from TEOS or silane, is deposited and planarized, as by CMP. A misaligned through-hole 55 is then formed in a conventional manner, after applying a photoresist mask and plasma etching. As shown in FIG. 5, misaligned through-hole 55 exposes a portion of the upper surface 151A of metal feature 51A and, due to the high plasma etching rate characteristics of HSQ, also exposes a major portion of the side surface 251A of metal feature 51A.
The formation of a large trench exposing a major portion of the side surface of a metal feature in forming a borderless via creates various problems, particularly during subsequent barrier metal deposition and contact plug fill. For example, it becomes increasingly difficult to deposit a barrier layer within high aspect ratio (height/width) openings, mandated by the reduction of design features to the range of 0.50 microns and under. A typical metal feature, such as features 51A and 51B, comprises a first lower metal layer of a refractory material such as tungsten or titanium, a primary intermediate metal layer such as aluminum or an aluminum alloy, and an upper anti-reflective coating which also serves as an etch stop. In forming a misaligned through-hole exposing a significant portion of the side surface 251A of metal feature 51A, undercutting would occur exposing a portion of the primary aluminum or aluminum alloy and rendering it very difficult to deposit a suitable conformal barrier layer material. Upon subsequent plug filling, as with tungsten from tungsten hexafluoride vapor, an undesirable interaction with aluminum sometimes occurs.
In copending application Ser. No. 08/951,592 filed on Oct. 16, 1997, a method is disclosed for restoring degradation of an HSQ film by exposure to an H.sub.2 -containing plasma to increase the number of Si--H bonds, decrease the number of Si--OH bonds, and decrease the propensity to absorb moisture. The disclosed treatment with an H.sub.2 -containing plasma enables the use of HSQ to gap fill metal lines and form borderless vias with improved reliability by reducing outgassing and, hence, void formation.
In copending application Ser. No. 08/924,131 filed on Sep. 5, 1997 (Our Docket No. 1033-350), a method is disclosed for depositing a titanium nitride barrier layer in a through-hole by chemical vapor deposition with subsequent plasma treatment in a plasma of hydrogen/nitrogen to decrease its carbon content.
In copending application Ser. No. 08/992,430 filed on Dec. 18, 1997, the etch rate of a deposited HSQ layer is decreased by selectively heating portions of the HSQ layer adjoining the upper and side surfaces of a lower conductive feature to increase the density and etching resistance vis-a-vis portions of the HSQ layer which do not adjoin the conductive feature.
There exists a need to form interconnection patterns having borderless vias employing HSQ as a gap fill layer with improved reliability and increased production throughput. There exists a particular need for improving the etching resistance of an HSQ gap fill layer to avoid exposing side surfaces of a lower metal feature, thereby forming interconnection patterns exhibiting improved reliability.